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TSMC takes 40nm to volume
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18/11/2008
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TSMC has moved its 40nm general purpose (G) and low power (LP) processes into volume production. Announced in March, the 40G process targets performance driven applications, whilst the 40LP process is aimed at low power applications.
“We view 40nm as an important process node for the cost effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes,” said Rick Bergman, general manager of AMD’s graphics products group.
The 40G and 40LP processes passed process qualification, reaching ‘first wafers out’ status in October, when the first customer wafers entered production.
“While timed to respond to the technical requirements of our broad customer base, the two processes are clearly the right manufacturing processes at the right time and can help the semiconductor industry – and conceivably other portions of the global economy – to innovate out of the current downturn,” said Jason Chen, vp, worldwide sales and marketing, TSMC.
According to TSMC, the 40G process is up to 30% faster than its 65nm GP process at the same leakage, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than the 65LP at the same speed.
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Author
Graham Pitcher
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