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Communications systems go!
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07/11/2008
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Many integrated circuit designers wake up at night with nightmares involving mixed signal design and a classic example involves the design of high speed serialisers and deserialisers (serdes).
If a process is selected which will allow good performance on the analogue sections of the design – for example, phase locked loops, cable drivers and very high speed sections – then there is invariably a compromise in cost and power when it comes to the digital section.
Meanwhile, if a process is selected with an eye to low cost and low power dissipation, then the resulting small transistors struggle to meet analogue requirements. If the ic designers don’t manage to do a good job of their task, then the nightmares are passed on to the equipment and system designers.
One way to avoid these problems is to partition the task in such a way that the bulk of the analogue tasks are housed on one chip and that chip is manufactured using a process optimised for analogue performance. The digital functions, meanwhile, should be placed on a different piece of silicon. This is the concept behind the ‘FPGA Attach’ video serdes products recently released by National Semiconductor.
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Author
Mark Sauerwald
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